1. Field of the Invention
The present invention relates to a so-called single bit line semiconductor memory wherein a bit line is precharged to a predetermined potential and then discharged according to memory data, whereby reading of the data is accomplished.
2. Description of the Prior Art
The single bit line semiconductor memory performs reading of data by precharging a bit line to a predetermined potential and then discharging the bit line according to memory data (for example, U.S. Pat. No. 5,880,990). A semiconductor memory of this type includes a sense amplifier SA which has an inverter INVSA1 and a PMOS transistor PTSA1 as shown in FIG. 4 of the publication of this patent. When reading data which is supposed to be read such that output data DATA is at L (Low) level, the PMOS transistor PTSA1 maintains the bit lint potential at H (High) level.
However, in the semiconductor memory having the PMOS transistor PTSA1 as described above, when reading data which is supposed to be read such that the bit line potential transitions to L level, the bit line potential is prevented from decreasing because the PMOS transistor PTSA1 serves to maintain the bit line potential at H level at the time of precharging the bit line. This deteriorates the reading speed. This problem is especially critical when the supply voltage is decreased.